In the formation of integrated circuits, it is often necessary to etch an aperture in a silicon substrate. In the past this substrate etch was used to define apertures which were filled with dielectric in order to provide isolation between adjacent devices. There was no particular criticality associated with the slope of the sidewalls of these apertures. Moreover, these apertures were not particularly deep (e.g., 2-3 .mu.m).
In semiconductor memory technology, the trend toward packing more memory cells into a given chip area has led to the development of "three dimensional" or "trench" memory cells. In these cells, the charge plate of the storage capacitor is formed by one or more polysilicon layers and one or more dielectric layers that are coated within a deep (e.g., 5-6 .mu.m) trench. The sidewalls of these deep trenches must be substantially vertical (i.e., have a slight positive taper x, where 88.degree.&lt;x&lt;90.degree.) in order to (a) minimize the amount of chip space consumed by the trench, and (b) present a topology that can be reliably coated with conductive and insulative films. Any etch process that is used to form deep trenches in silicon must provide a maximum "aspect ratio" (i.e., the vertical dimension of the trench should be at a maximum as compared to the horizontal dimension) while minimizing "etch bias" (i.e., the horizontal dimension of the trench should not be appreciably greater than the horizontal dimension of an aperture formed in a masking layer through which the trench is etched).
An article by Schaible et al, entitled "Reactive Ion Etching of Silicon," IBM Technical Disclosure Bulletin, Vol. 22, No. 5, October 1979 p. 1819, discloses the general idea of forming a trench in silicon by utilizing a Cl.sub.2 /Ar reactive ion etch ("RIE") chemistry. By adding CCl.sub.4 to the etch gas, a larger amount of Cl.sub.2 can be used to increase the silicon etch rate without causing lateral etching of an n-type subcollector region.
U.S. Pat. 4,222,792 (issued 9/16/80 to Lever et al and assigned to the assignee of the present invention) discloses a process of forming a trench isolation region. The patent lists various techniques of forming a trench in a silicon substrate, namely Cl.sub.2 /Ar or CCl.sub.4 /Ar based RIE, fluorine based RIE such as CF.sub.4, sputter etching or ion milling.
U.S. Pat. 4,417,947 (issued 11/29/83 to Pan and assigned to Signetics Corp.) relates to a process of controlling the slope of apertures formed in silicon by varying the oxygen content of a CCl.sub.4 /O.sub.2 RIE. An anisotropic profile is achieved when there is no oxygen present.
U.S. Pat. 4,450,042 (issued 5/22/84 to Purdes and assigned to Texas Instruments) discloses a BCl.sub.3 /Br.sub.2 plasma chemistry for anisotropic etching of silicon and silicon-containing compounds such as silicide. In general, the etch rate increased with increasing He (inert ion bombardment) in the presence of 8% BCl.sub.3. The addition of bromine was found to be critical in that it passivated the sidewalls to increase the verticality of the etch.
U.S. Pat. 4,475,982 (issued 10/9/84 to Lai et al and assigned to the assignee of the present invention) relates to etching trenches through differentially-doped regions in a silicon substrate. Specifically, a CCl.sub.2 /argon RIE is used to etch lightly-doped regions, and a CCl.sub.2 F.sub.2 /oxygen RIE is used to etch more heavily-doped regions.
U.S. Pat. 4,569,718 (issued 2/11/86 to Butherus et al and assigned to AT&T) teaches the use of a BCl.sub.3 /Cl.sub.2 etch chemistry to etch gallium arsenide.
As shown in the above art, the use of chlorine-based chemistries to etch trenches in silicon is known. However, it would be advantageous to have a particular chlorine-based etch chemistry that presents a maximum aspect ratio and a minimum etch bias for deep trenches formed in a silicon substrate.